Bayerischer
Forschungsverbund für Nanoelektronik (FORNEL)
3rd FORNEL Workshop on
Nanoelectronics
Erlangen,
March 27, 2007
Workshop Flyer
Presentations
Presentation
of FORNEL
H. Ryssel, University of Erlangen-Nuremberg and Fraunhofer IISB,
Erlangen
Physics-Based Modeling of Quantum
Transport in Nanostructured Devices
A. Heigl, G. Wachutka, Technical University of Munich
Simulation of CMOS
Nanotransistors
A. Burenkov, Fraunhofer IISB, Erlangen
Simulation of the Silicon Tunnel
FET
K. Boucart, EPFL Lausanne, Switzerland
Ab-Initio Assisted Process and
Device Simulation for Nanoelectronic
Devices
W. Windl, Ohio State University, USA
Memory Concepts for Sub-50nm
Technology Generations
T. Mikolajick, Technical University of Freiberg
Analog Circuit Design with
Multi-Gate and Tunneling FETs
M. Fulde, M. Weis, G. Knoblinger, D. Schmitt-Landsiedel, Technical
University of Munich
Compact Logic Gates with
Electron Y-Branch Switches
L. Worschech, D. Hartmann, A. Forchel, University of Würzburg
Scanning Force Microscopy for Process and Device Characterization
O. Krause, NanoWorld Services GmbH, Erlangen
Optimization of the Quartz
Template Fabrication for UV Nanoimprint
Lithography
H. Schmitt, University of Erlangen-Nuremberg
Projection Mask-Less
Nano-Lithography (PML2) and Nano-Patterning (PMLP)
for Nanoelectronics
H. Loeschner, E. Platzgummer, IMS Nanofabrication AG, Vienna,
Austria
A Comparative Study of ALD Grown High-k Dielectrics Using Ozone and
Water as Oxidant
F. Speck, University of Erlangen-Nuremberg
In-situ Monitoring and Optimization of ALD Processes
V. Rangelov, ATV Technologie GmbH, Vaterstetten
Cleaning Methods for Silicon
Surfaces
A. Aßmuth, Bundeswehr University, Munich
Quantitative Determination of
Oxide Charge and Interface State Density
by Photocurrent Analysis
M. Rommel, Fraunhofer IISB, Erlangen
[Home]
[Impressum]